IIT Delhi micro-GPU, in plain words: what students should do this week

IIT Delhi micro-GPU news on 24 September 2026 is not a new gaming card you can buy this Diwali. It is a small graphics chip design, written by two M.Tech students and two professors in Electrical Engineering, that can draw pictures on a cheap display board. The official note is on IIT Delhi’s site. Read that first if a coaching page starts shouting about “India beating Nvidia”.

If the words below feel new, read this block once. A GPU is a chip that draws images and does many small sums at the same time. Your phone and laptop already have one. Most of those chips are designed and made outside India. A micro-GPU here means a small version meant for simple screens, not for ChatGPT training. An FPGA is a practice board you can rewire with code. An ASIC is a real chip cut in a factory. RTL is the language used to describe the chip before it becomes hardware. None of this is a placement offer.

What IIT Delhi actually showed on 24 September 2026

The Electrical Engineering team — M.Tech students Nammi Akash and M. Ravi Teja, with Prof. Jayadeva and Prof. Kaushik Saha — showed programmable graphics rendering on a Xilinx Spartan-7 FPGA. The engine is a custom floating-point GPU written fully in RTL. The institute’s own line is that, to their knowledge, this is the first working, demonstrable indigenously designed micro-GPU from a university in India.

The uses they listed are not data-centre AI. They listed industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers, and other cheap embedded screens. That list matters. It tells you the size of the problem they picked: a screen that must stay cheap, not a 16 GB laptop GPU.

Next on their own roadmap: an 8–16 core vector-style graphics processor, a compiler and graphics software toolchain, and later a proof of concept on a 65 nm ASIC node. They also said they will look for funding for ASIC work, system integration and eventual commercial use. That last line is a plan, not a product on Amazon.

Prof. Jayadeva said the work shows the teaching and research value of indigenous programmable graphics hardware on a standard FPGA board. Prof. Saha said the project forces students to join arithmetic hardware, programmable architectures, compilers and embedded systems in one frame. Those are lab sentences. Treat them as a syllabus hint, not as a job guarantee.

Who this page is for — and who should skip

Use this page if you are in Class 12 and choosing between ECE, EE, CS or a “AI and Data Science” brochure; if you already sit in ECE/EE/CS and need a weekend project that interviewers can open; or if you are hunting chip-design internships after Semicon India week.

Skip it if you want a cheaper RTX card this month. This board will not run your games. Skip it if your only plan is to paste the IIT Delhi headline into a LinkedIn post with no lab work behind it. Skip it if you need a notification with a last date — this is a research note, not a recruitment PDF.

• Class 12: learn what FPGA and RTL mean. Do not change your JEE rank list because of one lab demo.
• 2nd–3rd year ECE/EE: one small Verilog or VHDL block on a cheap FPGA is worth more than ten “semiconductor interest” lines on a CV.
• CS students: compilers and graphics toolchains are the other half of this story. Hardware without software stays a slide.
• Final year: check official internship boards, not WhatsApp “chip internship 2026, pay Rs 499” forms.

What you can do in the next seven days

1. Open the official IIT Delhi note and write four lines in your own words: who, what board, what it is not, what they want to build next. Keep the URL. That is your interview answer if someone asks about “indigenous GPU”.

2. If you already have access to a college FPGA kit or a cheap used Spartan / Artix board, pick one tiny task: blink a pattern, draw a rectangle, or write a 4-bit adder in Verilog. Finish it. Screenshot the waveform. That file is the proof of work. A news headline is not.

3. Bookmark two official doors, not aggregator blogs: the India Semiconductor Mission site at ism.gov.in and the C2S internship page if your college is on that network. Dates move. Read the last-date line before you mail your HOD.

4. Read the Campus Reality Semicon India companion if you missed that week: Semicon India 2026: what students should do. The money headlines there and this FPGA demo are the same industry. One is a policy event. One is a student project that actually compiled.

5. If you sit placements in core ECE, add one honest line to your project README: language (Verilog/VHDL), board name, what the testbench checked, what still fails. “Worked on VLSI” is not an answer. “Drew a rectangle on Spartan-7, testbench in X minutes” is an answer.

What this is not

It is not proof that India now makes Nvidia-class chips. Nvidia and AMD sell products at a different scale, on different process nodes, with years of software stacks. A 65 nm proof of concept, if it happens, is still a teaching and embedded-display chip. Mature nodes can be the right choice for cheap dashboards. They are the wrong comparison for a 4 nm AI accelerator.

It is also not a reason to pay a private institute for a “GPU design certificate” this weekend. The IIT Delhi note names a department, two students and two professors. It does not name a paid coaching partner. If a form asks for a registration fee to “join the IIT Delhi GPU mission”, close the tab.

Open internships that are actually live this month sit on the Campus Reality board: internships. DRDO and DoT windows on that page have printed last dates. This GPU story does not replace those forms.

A short map from Class 12 to a lab bench

Class 12 physics already has current, voltage and digital logic at a basic level. That is enough to understand why an FPGA is a bag of logic gates you can rearrange. First-year engineering adds Boolean algebra and a hardware description language. Second year is when a student can finish a small RTL block without copying a full GitHub repo. Third year is when a compiler or a display pipeline becomes a real project instead of a seminar topic.

If you are outside IIT Delhi, you do not need their exact board. You need one finished block, one test, and one paragraph that admits what you did not finish. Faculty will smell a copied “micro-GPU” title from a kilometre away.

Source to keep: the IIT Delhi news page dated 24 September 2026, IIT Delhi Researchers Develop First Indigenously Designed Micro-Graphics Processing Unit. If that page and a YouTube thumbnail disagree, the institute page wins.